Using Local TCM Instead of Cache — Simplicity Focus

Executive Summary

Local Tightly-Coupled Memory (TCM) is a small, directly-attached SRAM region that provides deterministic, single-cycle or few-cycle access with a straightforward programming model. This case study explains why choosing local TCM for critical code and data often simplifies hardware, software, verification, and system bring-up compared to relying entirely on hardware-managed caches.

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Context & Problem

Caches improve average performance but introduce architectural complexity through tag arrays, replacement policies, coherence mechanisms, unpredictable miss penalties, and hidden performance cliffs. In safety-critical and real-time systems, these unpredictable behaviors significantly increase verification effort and timing analysis complexity.

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Decision Drivers

TCM was selected because of its deterministic latency characteristics, simpler hardware implementation, reduced software overhead, and easier debug visibility. By eliminating cache maintenance operations and coherence corner cases, the development team achieved faster bring-up and more predictable execution timing.

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Recommended Implementation Pattern

The implementation reserved dedicated TCM regions for interrupt service routines, context-switch handlers, fast processing loops, and latency-sensitive data structures. Large bulk data and non-critical workloads remained in cacheable memory regions. Software-managed data movement using DMA and explicit memory copies enabled controlled working-set placement.

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Linker Configuration Strategy

Custom linker sections such as .tcm_text and .tcm_data were introduced to simplify placement of deterministic code paths directly into TCM regions during build time. This allowed critical software components to execute immediately during boot without requiring cache enablement or MMU initialization.

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Verification & Bring-Up Advantages

Using TCM significantly reduced micro-architectural corner cases during simulation and verification. The deterministic single-beat access behavior eliminated the need to validate cache coherence interactions, replacement policy edge cases, and variable latency timing paths. Worst-case execution time analysis became substantially easier for functional safety certification workflows.

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Physical & System Considerations

Although TCM consumes valuable on-chip SRAM resources, careful working-set analysis ensured efficient utilization. The design also supported banked TCM organization to enable parallel access paths and improved scalability for multi-master embedded workloads.

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Trade-offs

TCM requires explicit software management and can lead to unused memory capacity if poorly partitioned. Traditional cache hierarchies remain more efficient for large, general-purpose applications with dynamic working sets. For shared CPU and peripheral data flows, explicit synchronization and software-managed movement strategies were necessary.

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Conclusion

A hybrid memory strategy combining TCM for latency-critical execution paths and cacheable memory for bulk processing provided the best balance between simplicity, determinism, and overall performance. The approach simplified the hardware-software contract while reducing verification complexity and improving real-time predictability.