Senior ASIC Design Engineer
Lead complex ASIC design projects from architecture to tape-out. Work with cutting-edge process technologies and develop next-generation semiconductor solutions.
Key Qualifications:
Minimum of 2 years experience in ASIC design.
Experience with cutting-edge process nodes (7nm or smaller).
Master's or Doctorate in Electrical Engineering is preferred.
Skilled in Verilog/SystemVerilog and synthesis techniques.
Strong understanding of timing closure and physical design principles.
Your Responsibilities:
Design and validate intricate digital ASICs.
Enhance designs for efficiency in power, performance, and area.
Master's or Doctorate in Electrical Engineering is preferred.
Skilled in Verilog/SystemVerilog and synthesis techniques.
Strong understanding of timing closure and physical design principles.
Benefits and Perks:
Minimum of 2 years experience in ASIC design.
Experience with cutting-edge process nodes (7nm or smaller).
Master's or Doctorate in Electrical Engineering is preferred.
Skilled in Verilog/SystemVerilog and synthesis techniques.
Strong understanding of timing closure and physical design principles.